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The table below details the sector protection status for various scenarios of the WP pin, the
Enable Sector Protection command, and the Disable Sector Protection command.
W P
Time
1
2
3
Period
1
2
3
WP Pin
High
High
High
Low
High
High
High
Enable Sector Protection Command
Command Not Issued Previously
Command Issued
–
x
Command Issued during Period 1 or 2
–
Issue Command
Disable Sector Protection Command
x
–
Command Issued
x
Not Issued Yet
Command Issued
–
Sector Protection Status
Disabled
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
7.4.6
7.4.7
RESET
READY/BUSY
A low state on the reset pin (RESET) will terminate the operation in progress and reset the inter-
nal state machine to an idle state. The device will remain in the reset condition as long as a low
level is present on the RESET pin. Normal operation can resume once the RESET pin is brought
back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore,
in low pin count applications, connection of the RESET pin is not necessary if this pin and fea-
ture will not be utilized. However, it is recommended that the RESET pin be driven high
externally whenever possible.
This open drain output pin will be driven low when the device is busy in an internally self-timed
operation. This pin, which is normally in a high state (through an external pull-up resistor), will be
pulled low during programming/erase operations, and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed. During Page
Erase and Block Erase, read and write operations can be performed to both buffers.
16
AT45DB321C
3387M–DFLASH–2/08
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